Package substrate having embedded capacitor

ABSTRACT

A package substrate having embedded capacitor is provided. The package substrate includes a first core circuit board, at least one embedded capacitor, a second core circuit board and a dielectric layer. At least one metal layer is disposed on a surface of the first core circuit board and at least one first conductive through hole of the first core circuit board is connected to the metal layer. The embedded capacitor is embedded in the first core circuit board and connected to the metal layer. A wiring layer is disposed on a surface of the second core circuit board and at least one second conductive through hole of the second core circuit board is connected to the wiring layer. The dielectric layer is laminated between the first and the second core circuit boards.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 95141129, filed Nov. 7, 2006. All disclosure of the Taiwanapplication is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a package substrate, and moreparticularly to a package substrate having embedded capacitor.

2. Description of Related Art

Embedded capacitor can be integrated into a package substrate in thesame fabrication process to enhance the efficiency of the activecomponents inside an electronic package, improve electrical performanceand lower assembling cost. Therefore, it has become the mainstreammethod for fabricating electronic carrier. At present, the developmentof embedded capacitor is mainly aiming toward small size ceramiccapacitors. In general, ceramic capacitors can be classified into singlelayer ceramic capacitors (SLCC) and multi-layer ceramic capacitors(MLCC), also known as discrete capacitors. However, because thecapacitance of the conventional discrete capacitor is low and has a lowdielectric constant, they could hardly enhance the performance of aconventional circuit substrate.

FIG. 1 is a schematic diagram of a conventional package substrate havingembedded capacitor. The internal structure of the package substrate 100and its fabrication process are roughly as follows. First, a core board110, a plurality of dielectric materials 121˜124 and two copper foils142 and 144 soldered with a plurality of discrete capacitors 130 areprovided. Then, the dielectric materials 121˜124 and the two copperfoils 142 and 144 having the discrete capacitors 130 are aligned andcompressed to the core board 110. Thus, the two copper foils 142 and 144and the discrete capacitors 130 are located between the upper dielectricmaterials 121, 122 and the lower dielectric materials 123, 124respectively to form a core laminated board 160. Thereafter, amechanical drilling process is performed to form a plurality ofconductive through holes 150 inside the core laminated board 160 thataverts the discrete capacitors 130 and connects the upper and lowercopper foils 142 and 144. In addition, a surface circuit 162 of the corelaminated board 160 can connect with the discrete capacitors 130 throughthe via hole 164.

Because the discrete capacitors 130 have to avert the conductive throughhole 150, the usable area and location for disposing the capacitors 130are constrained by the number and locations of the conductive throughholes 150 and the degree of freedom of disposing the capacitors 130 islowered. In the meantime, the discrete capacitors 130 are easily damagedor broken in the process of compressing the substrate. As a result, thereliability of the capacitors 130 is lowered.

SUMMARY OF THE INVENTION

Accordingly, the present invention directs to a package substrate havingembedded capacitor for enhancing the space and degree of freedom ofdisposing the embedded capacitor.

The present invention also directs to a package substrate havingembedded capacitor such that the performance of the package substrate isenhanced by using a dielectric material with high dielectric constantand low dielectric loss.

The present invention directs to a package substrate having embeddedcapacitor such that the embedded capacitor is protected from damage bycovering it with a passivation layer.

The present invention provides a package substrate having embeddedcapacitor. The package substrate includes a core circuit board, at leastone dielectric layer, at least one embedded capacitor and at least onemetal layer. At least one wiring layer is disposed on a surface of thecore circuit board and a conductive through hole of the core circuitboard is connected to the wiring layer. In addition, the dielectriclayer covers the wiring layer and has at least one via hole.Furthermore, the embedded capacitor is connected to the metal layer andis embedded within the dielectric layer. The metal layer covers thedielectric layer and connects to the wiring layer through the via hole.

The present invention also provides a package substrate having embeddedcapacitor. The package substrate includes a first core circuit board, atleast one embedded capacitor, a second core circuit board and adielectric layer. At least one metal layer is disposed on a surface ofthe first core circuit board and at least one first conductive throughhole of the first core circuit board is connected to the metal layer. Inaddition, the embedded capacitor is embedded within the first corecircuit board and connected to the metal layer. A wiring layer isdisposed on a surface of the second core circuit board and at least onesecond conductive through hole of the second core circuit board isconnected to the wiring layer. Furthermore, the dielectric layer islaminated between the first core circuit board and the second corecircuit board.

The present invention also provides a package substrate having embeddedcapacitor. The package substrate includes a core circuit board, at leastone embedded capacitor, at least one dielectric layer and at least onewiring layer. At least one metal layer is disposed on a surface of thecore circuit board and at least one conductive through hole of the corecircuit board is connected to the metal layer. In addition, the embeddedcapacitor is embedded within the core circuit board and connected to themetal layer. The dielectric layer covers the wiring layer and has anembedded hole. Furthermore, the wiring layer covers the dielectric layerand is electrically connected to the embedded hole.

According to an embodiment of the present invention, the packagesubstrate further includes a first passivation layer covering theembedded capacitor. In addition, the metal layer has an opening and theopening exposes a surface of the embedded capacitor. The packagesubstrate further includes a second passivation layer covering thesurface of the embedded capacitor. The first passivation layer isfabricated using epoxy resin or polyimide, and the second passivationlayer can be fabricated using epoxy resin or polyimide too.

According to an embodiment of the present invention, the packagesubstrate further includes at least one surface wiring layer disposed ona surface of the package substrate. The surface wiring layer has atleast one contact electrically connected to the metal layer or thewiring layer. In addition, the package substrate further includes asolder mask layer covering the surface wiring layer. The solder masklayer has at least one opening that exposes the contact.

The present invention also provides a package substrate having embeddedcapacitor. The package substrate includes a core board, an embeddedcapacitor, a first passivation layer and a metal layer. The embeddedcapacitor is embedded within the core board and the first passivationlayer covers the embedded capacitor. In addition, the metal layer coversthe core board and is connected to the embedded capacitor.

According to an embodiment of the present invention, the metal layer hasan opening and the opening exposes a surface of the embedded capacitor.The package substrate further includes a second passivation layercovering the surface of the embedded capacitor. The first passivationlayer is fabricated using epoxy resin or polyimide, and the secondpassivation layer can be fabricated using epoxy resin or polyimide too.

Due to the improvement in the substrate structure, the embeddedcapacitor in the present invention can be disposed in a suitablelocation without having to avert the conductive through hole. Therefore,the space and degree of freedom for disposing the embedded capacitors isenhanced. In addition, capacitors fabricated using high dielectricconstant and low dielectric loss material such as polymer-ceramiccomposite can be used instead of the conventional discrete capacitors soas to enhance the performance of the package substrate. Furthermore, theembedded capacitors of the present invention is covered with at leastone passivation layer to prevent the embedded capacitors from receivingpossible damage in the process of compressing the substrate. Hence,overall reliability of the package substrate is improved.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a schematic diagram of a conventional package substrate havingembedded capacitor.

FIG. 2 is a schematic diagram of a portion of a package substrate havingembedded capacitor according to a first embodiment of the presentinvention.

FIG. 3 is a schematic diagram of a portion of a package substrate havingembedded capacitor according to a second embodiment of the presentinvention.

FIG. 4 is a schematic diagram of a portion of a package substrate havingembedded capacitor according to a third embodiment of the presentinvention.

FIG. 5 is a schematic diagram of a portion of a package substrate havingembedded capacitor according to a fourth embodiment of the presentinvention.

FIG. 6 is a schematic diagram of a portion of a package substrate usingthe substrate having embedded capacitor in FIG. 3 as the core layer.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

FIG. 2 is a schematic diagram of a portion of a package substrate havingembedded capacitor according to a first embodiment of the presentinvention. The package substrate 200 mainly includes a core circuitboard 210, a dielectric layer 220, at least one embedded capacitor 230and a metal layer 240. The core circuit board 210 is, for example, acopper foil substrate with glass fiber and epoxy resin serving asinsulating material so as to enhance the strength and support of thepackage substrate 200. In addition, the core circuit board 210 has atleast one conductive through hole 216. The method of forming theconductive through hole 216 includes, for example, performing amechanical drilling to form a through hole and then performing anelectrochemical plating to form a layer of conductive material on theinner sidewall of the through hole. As a result, the upper and lowercopper foils are connected through the conductive through hole 216.After an etching operation is performed to pattern the copper foils, awiring layer for transmitting signals is formed.

As shown in FIG. 2, the embedded capacitor 230 of the present inventionis disposed in the dielectric layer 220. The dielectric layer 220 mayinclude a first dielectric layer 222 and a second dielectric layer 224that covers a first wiring layer 212 and a second wiring layer 214 ofthe core circuit board 210 respectively. It should be noted that becausethe conductive through hole 216 has already formed in the core circuitboard 210 earlier on, there is no need to perform the process in asubsequent process. Therefore, the location of the conductive throughhole 216 will not affect the space for disposing the embedded capacitor.As shown in FIG. 2, the embedded capacitor 230 can be disposed in thefirst dielectric layer 222 underneath the conductive through hole 216.Since the disposition of embedded capacitor 230 is unaffected by theconductive through hole 216, the space and degree of freedom ofdisposing the embedded capacitor 230 are enhanced.

In the present embodiment, the embedded capacitors 230 can be discretecapacitors. The capacitors are pre-soldered to a metal layer 240 (forexample, a copper foil) and then the dielectric layer 220 and the metallayer 240 are compressed to the core circuit board 210 so that theembedded capacitor 230 is embedded in the dielectric layer 220.Obviously, epoxy-ceramic composite with high dielectric constant can beused as the embedded capacitor 230 to increase the capacitance. Themetal layer 240 may include a first metal layer 242 and a second metallayer 244. The first metal layer 242 covers the first dielectric layer222, and the first metal layer 242 can be connected to the first wiringlayer 212 through a conductive via 226 in the first dielectric layer222. In addition, the second metal layer 244 covers the seconddielectric layer 224, and the second metal layer 244 can be connected tothe second wiring layer 214 through a conductive via 228 in the seconddielectric layer 224.

As mentioned above, the conventional discrete capacitor has a relativelylow capacitance. In the present embodiment, epoxy resin-ceramiccomposite capacitor or other ceramic/polymer composite capacitor withhigh dielectric constant is used so that the capacitance is increasedand the dielectric loss is reduced. Hence, the performance of thepackage substrate 200 is enhanced.

In the present embodiment, a build-up method can be used to sequentiallyfabricate multiple layers of interconnect structures 250 after theprocess for assembling the embedded capacitor is completed so that theoriginal four circuit layer substrate is increased to six, eight, ten ortwelve circuit layer substrate. By drilling a plurality of blind holeswith laser and then filling the blind holes with conductive material,two neighboring wiring layers 252 are connected. Finally, a solder masklayer 260 covers a surface wiring layer 256 in the outermost layer ofthe package substrate 200. The solder mask layer 260 has at least oneopening 262 that exposes a contact of the surface wiring layer 256. Inthe present embodiment, a top contact 258a is used for electricallyconnecting to at least one chip or passive element (not shown), and abottom contact 258b is used for electrically connecting to a printedcircuit board (not shown). Hence, the package substrate 200 serves as asignal transmission medium between the top and bottom elements.

FIG. 3 is a schematic diagram of a portion of a package substrate havingembedded capacitor according to a second embodiment of the presentinvention. The package substrate 300 mainly includes a core board 310,at least one embedded capacitor 330, a first passivation layer 338 and ametal layer 340. The core board 310 is a substrate fabricated usingglass fibers and epoxy resin as its insulating material so as to enhancethe strength and support of the package substrate 300. In addition, theembedded capacitor 330 is embedded in the core board 310 andelectrically connected to the metal layer 340. In the presentembodiment, the embedded capacitor 330 can be an epoxy resin-ceramiccomposite capacitor or other ceramic/polymer composite capacitor withhigh dielectric constant formed on the metal layer 340 after performinga high-temperature sintering process. Afterwards, electrode materialcovers the dielectric material 332 to form an electrode 334 connected tothe metal layer 340.

To prevent the compressing process from breaking or damaging theembedded capacitors 330, the first passivation layer 338 is formed tocover the embedded capacitors 330 before compressing the substrate. Thefirst passivation layer 338 is fabricated from polymer material such asepoxy resin or polyimide. The first passivation layer 338 not only hashigher pressure resistant strength, but also has the characteristics ofpreventing the reactants of etching process, plating process and surfacetreatment process performed prior to the compression process fromaffecting the embedded capacitors 330 and their electrodes. In addition,the interior of an opening 342 on another side of the metal layer 340can be selectively filled with a second passivation layer 336 to cover asurface of the embedded capacitor 330. The material and function of thesecond passivation layer 336 are identical to the first passivationlayer 338 and similarly prevent the embedded capacitors 330 frompossible damage.

FIG. 4 is a schematic diagram of a portion of a package substrate havingembedded capacitor according to a third embodiment of the presentinvention. The package substrate 400 mainly includes a first corecircuit board 410, a dielectric layer 420, at least one embeddedcapacitor 430 and a second core circuit board 440. The first and secondcore circuit boards 410 and 440 are, for example, copper foil substratesusing glass fiber or epoxy resin as the insulating material so as toenhance the strength and support of the package substrate 400. Inaddition, the dielectric layer 420 can be cured or semi-cured glassfiber epoxy resin laminated between the first and the second corecircuit board 410 and 440. In the present embodiment, the two opposingsurfaces of the first core circuit board 410 have a metal layer 412 andat least one first conductive through hole 414 of the first core circuitboard 410 is connected to the metal layer 412. The embedded capacitor430 is embedded in the first core circuit board 410 and connected to themetal layer 412. Similarly, the two opposing surfaces of the second corecircuit board 440 have a wiring layer 442 and at least one secondconductive through hole 444 of the second core circuit board 440 isconnected to the wiring layer 442.

As described in above, the embedded capacitors 430 in the presentembodiment can be epoxy resin-ceramic composite capacitors or otherceramic/polymer composite capacitors with high dielectric constant so asto enhance the performance of the package substrate 400. Furthermore,before compressing the substrate, the first passivation layer 338 inFIG. 3 can be used to cover the embedded capacitors 430 in FIG. 4.Similarly, the second passivation layer 336 can be used to fill theopening 416 on the other side of the metal layer 412 to protect theembedded capacitors 430 and their electrodes.

Similarly, as shown in FIG. 4, a conductive through hole 450 connectingthe metal layer 412 and the wiring layer 442 can be formed in thepackage substrate 400 of the present invention by mechanically drillingto form a through hole and performing an electrochemical plating processto form a conductive layer on the inner sidewall of the through hole.Obviously, the conductive through hole 450 can be filled with insulatingor conductive filling material 452 according to the thickness of thepackage substrate 400 whose details are omitted. In addition, a build-upmethod or other process can be used to sequentially fabricate multiplelayers of interconnect structures (not shown) according to the circuitrequirements after the process for forming the embedded capacitors 430is completed. Furthermore, a solder mask layer covers the outermostsurface wiring layer like the one in FIG. 1. The solder mask layer hasat least one opening exposing a contact on the surface wiring layer sothat the package substrate 400 serves as a signal transmission mediumbetween the top and bottom elements.

FIG. 5 is a schematic diagram of a portion of a package substrate havingembedded capacitor according to a fourth embodiment of the presentinvention. The package substrate 500 mainly includes a core circuitboard 510, at least one dielectric layer 520, at least one embeddedcapacitor 530 and at least one wiring layer 540. The core circuit board510 is, for example, a copper foil substrate fabricated using glassfibers and epoxy resin so as to enhance the strength and support of thepackage substrate 500. In addition, the dielectric layer 520 can becured or semi-cured epoxy resin or polyimide covering the core circuitboard 510 using a build-up method. In the present embodiment, the twoopposing surfaces of the core circuit board 510 have a metal layer 512and at least one conductive through hole 514 of the core circuit layer510 connected to the metal layers 512. The embedded capacitors 530 areembedded in the core circuit board 510 and connected to the metal layers512.

In the present embodiment, the dielectric layer 520 can be a singlelayer or multiple layers and the wiring layer 540 can be a single layeror multiple layers. Using multiple layers as an example, the dielectriclayer 520 has a plurality of laser-drilled and conductive materialfilled via holes 522 for electrically connecting neighboring upper andlower wiring layers 540. Obviously, the wiring layer 540 can beconnected to one of the metal layers 512 through the via hole 524.Alternatively, the metal layers 512 are connected to the wiring layer540 through a through hole 550 passing through the core circuit board510, the dielectric layer 520 and the wiring layer 540 of the packagesubstrate 500.

As described in above, the embedded capacitors 530 in the presentembodiment can be epoxy resin-ceramic composite capacitors or otherceramic/polymer composite capacitors with high dielectric constant so asto enhance the performance of the package substrate 400. Furthermore,before compressing the substrate, the first passivation layer 338 inFIG. 3 can be used to cover the embedded capacitors 530 in FIG. 5 (notshown) Similarly, the second passivation layer 336 can be used to fillthe opening 516 on the other side of the metal layer 512 to protect theembedded capacitors 530 and their electrodes.

Similarly, a build-up method or other process can be used tosequentially fabricate multiple layers of interconnect structures (notshown) according to the circuit requirements after the process forforming the embedded capacitors 530 is completed. Furthermore, a soldermask layer covers the outermost surface wiring layer like the one inFIG. 1. The solder mask layer has at least one opening exposing acontact on the surface wiring layer so that the package substrate 500serves as a signal transmission medium between the top and bottomelements.

FIG. 6 is a schematic diagram of a portion of a package substrate usingthe substrate having embedded capacitor in FIG. 3 as the core layer.After the process for assembling the embedded capacitors 330 iscompleted, a build-up method or other process can be used tosequentially fabricate multiple layers of interconnect structures 602 onthe package substrate 600 according to the circuit requirements. Theinterconnect structure 602 includes at least one dielectric layer 610and at least one wiring layer 620. Using multiple layers as an example,the dielectric layer 610 includes a plurality of first dielectric layers612 and a second dielectric layer 614. The first dielectric layer 612covers the first metal layer 340, and the second dielectric layer 614covers the core board 310 or second metal layer 344. In addition, thewiring layer 620 includes a plurality of first wiring layers 622, 624and a second wiring layer 626. The first wiring layers 622, 624 areconnected to each other through a via hole 616 in the first dielectriclayer 612. The second wiring layer 626 is connected to the second metallayer 344 through a via hole 618 in the second dielectric layer 614.Furthermore, at least one conductive through hole 628 can be used toconnect between the first wiring layers 622, 624 and the second wiringlayer 626.

In summary, the embedded capacitor in the present invention can bedisposed in a suitable location without having to avert the conductivethrough holes due to an improvement of the substrate structure.Therefore, the space and degree of freedom for disposing the embeddedcapacitors are enhanced. In addition, capacitors fabricated using highdielectric constant and low dielectric loss material such aspolymer-ceramic composite instead of the conventional discretecapacitors can be used so as to enhance the performance of the packagesubstrate. Furthermore, the embedded capacitors of the present inventionare covered with at least one passivation layer to prevent the embeddedcapacitors from receiving possible damage in the process of compressingthe substrate. Hence, overall reliability of the package substrate isimproved.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncovers modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A package substrate having embedded capacitor, comprising: a corecircuit board having at least one wiring layer, and the core circuitboard has at least one conductive through hole connected to the wiringlayer; at least one dielectric layer covering the wiring layer, and thedielectric layer has at least one conductive through hole; at least oneembedded capacitor, embedded in the dielectric layer; and at least onemetal layer covering the dielectric layer and connected to the embeddedcapacitor, wherein the metal layer is connected to the wiring layerthrough the conductive through hole.
 2. The package substrate of claim1, wherein the at least one embedded capacitor is disposed in a locationin the dielectric layer corresponding to the conductive through hole. 3.The package substrate of claim 1, wherein the at least one wiring layercomprises a first wiring layer and a second wiring layer disposed on twoopposing surface of the core circuit board.
 4. The package substrate ofclaim 3, wherein the at least one dielectric layer comprises a firstdielectric layer and a second dielectric layer, and the first dielectriclayer covers the first wiring layer and the second dielectric layercovers the second wiring layer.
 5. The package substrate of claim 4,wherein the at least one metal layer comprises a first metal layer and asecond metal layer, and the first metal layer covers the firstdielectric layer and the second metal layer covers the second dielectriclayer.
 6. The package substrate of claim 1, further comprising a firstpassivation layer that covers the embedded capacitor.
 7. The packagesubstrate of claim 1, wherein the metal layer has an opening thatexposes a surface of the embedded capacitor and the package substratefurther comprise a second passivation layer that covers the surface. 8.The package substrate of claim 6, wherein the first passivation layer ismade of epoxy resin or polyimide.
 9. The package substrate of claim 1,further comprising at least one surface wiring layer disposed on asurface of the package substrate, and the surface wiring layer has atleast one contact electrically connected to the metal layer.
 10. Thepackage substrate of claim 9, further comprising a solder mask layerthat covers the surface wiring layer and the solder mask layer has atleast one opening that exposes the contact.
 11. A package substratehaving embedded capacitors, comprising: a first core circuit boardhaving at least one metal layer, the first core circuit board has atleast one first conductive through hole connected to the metal layer; atleast one embedded capacitor, embedded in the first core circuit boardand connected to the metal layer; a second core circuit board having atleast one wiring layer, the second core circuit board has at least onesecond conductive through hole connected to the wiring layer; and adielectric layer, laminated between the first core circuit board and thesecond core circuit board.
 12. The package substrate of claim 11,wherein the at least one metal layer comprises a first metal layer and asecond metal layer disposed on two opposing surfaces of the first corecircuit board.
 13. The package substrate of claim 11, wherein the atleast one wiring layer comprises a first wiring layer and a secondwiring layer disposed on two opposing surfaces of the second corecircuit board.
 14. The package substrate of claim 11, further comprisinga passivation layer that covers the embedded capacitor.
 15. The packagesubstrate of claim 11, wherein the metal layer has an opening thatexposes a surface of the embedded capacitor and the package substratefurther comprise a second passivation layer that covers the surface. 16.The package substrate of claim 11, further comprising at least oneconductive through hole that passes through the first core circuitboard, the dielectric layer and the second core circuit board andconnects the metal layer and the wiring layer.
 17. The package substrateof claim 11, further comprising at least one surface wiring layerdisposed on a surface of the package substrate, the surface wiring layerhas at least one contact electrically connected to the metal layer orthe wiring layer.
 18. The package substrate of claim 17, furthercomprising a solder mask layer that covers the surface wiring layer andthe solder mask layer has at least an opening that exposes the contact.19. A package substrate having embedded capacitors, comprising: a corecircuit board having at least one metal layer, and the core circuitboard has at least one conductive through hole connected to the metallayer; at least one embedded capacitor, embedded in the core circuitboard and connected to the metal layer; at least one dielectric layercovering the core circuit board, and the dielectric layer has anembedded hole; and at least one wiring layer covering the dielectriclayer and connected to the embedded hole.
 20. The package substrate ofclaim 19, wherein the at least one metal layer comprises a first metallayer and a second metal layer disposed on two opposing surfaces of thecore circuit board.
 21. The package substrate of claim 19, furthercomprising at least one through hole that passes through the corecircuit board, the dielectric layer and the wiring layer and connectsthe metal layer and the wiring layer.
 22. The package substrate of claim19, further comprising a first passivation layer that covers theembedded capacitor.
 23. The package substrate of claim 19, wherein themetal layer has an opening that exposes a surface of the embeddedcapacitor, and the package substrate further comprises a secondpassivation layer that covers the surface.
 24. The package substrate ofclaim 19, further comprising at least one surface wiring layer disposedon a surface of the package substrate, the surface wiring layer has atleast one contact electrically connected to the metal layer or thewiring layer.
 25. The package substrate of claim 24, further comprisinga solder mask layer that covers the surface wiring layer, and the soldermask layer has at least one opening that exposes the contact.
 26. Apackage substrate having embedded capacitors, comprising: a core board;an embedded capacitor, embedded in the core board; a first passivationlayer covering the embedded capacitor; and a metal layer covering thecore board and connected to the embedded capacitor.
 27. The packagesubstrate of claim 26, further comprising: at least one dielectric layercovering the metal layer, and the dielectric layer has at least oneconductive through hole; and at least one wiring layer covering thedielectric layer, and connected to the conductive through hole.
 28. Thepackage substrate of claim 27, further comprising at least oneconductive through hole that passes through the core board, the metallayer, the dielectric layer, the wiring layer and connects the metallayer and the wiring layer.
 29. The package substrate of claim 26,wherein the first passivation layer is made of epoxy resin or polyimide.30. The package substrate of claim 26, wherein the metal layer has anopening that exposes a surface of the embedded capacitor, and thepackage substrate further comprises a second passivation layer thatcovers the surface.
 31. The package substrate of claim 30, wherein thesecond passivation layer is made of epoxy resin or polyimide.